Conventionally, as a non-volatile semiconductor memory device, a non-volatile semiconductor memory device that writes data by storing a charge in a charge storage layer in a memory cell by a quantum tunnel effect, for example, has been known (see, e.g., Patent Literature 1 and Non Patent Literature 1). FIG. 13 illustrates a conventional non-volatile semiconductor memory device 501, which includes a plurality of P-type memory wells W503a, W503b, W503c, and W503d arranged in a row direction (horizontal direction), for example, and has a configuration in which a plurality of memory cells C are formed in a matrix in each of the P-type memory wells W503a to W503d. In this non-volatile semiconductor memory device 501, a plurality of common word lines 502a, 502b, 502c, 502d, 502e, and 502f extending in the row direction are arranged with equal spacing in a column direction (vertical direction), and the common word lines 502a to 502f and the P-type memory wells W503a to W503d are arranged to respectively intersect each other.
The plurality of memory cells C arranged in the same row over the plurality of P-type memory wells W503a to W503d are connected to each of the common word lines 502a to 502f. A predetermined gate voltage can be uniformly applied to control gates of all the memory cells C arranged in the same row. Each of the P-type memory wells W503a to W503d is provided with a plurality of first bit lines L1 extending in the column direction and a plurality of second bit lines L2 similarly extending in the column direction.
Each of the P-type memory wells W503a to W503d has a configuration in which the one first bit line L1 and the second bit line L2 adjacent to the first bit line L1 are paired with each other and the plurality of memory cells C are arranged in parallel between the first bit line L1 and the second bit line L2 that run parallel to each other. In practice, each of the memory cells C has its one end connected to the first bit line L1 and has the other end connected to the second bit line L2. A writing voltage or a writing inhibition voltage, for example, can be applied to the one end and the other end, respectively, from the first bit line L1 and the second bit line L2.
All the memory cells C have the same configuration, and are N-channel type memory cells respectively having the P-type memory wells W503a to W503d as semiconductor substrates. Each of the memory cells C has a channel region between the one end and the other end formed with predetermined spacing in the semiconductor substrate (the p-type memory well W503a), for example, and has a configuration in which a charge storage layer, an interlayer insulating layer, and a control gate are sequentially stacked via a tunnel insulating layer on the channel region. Due to a voltage difference between a voltage applied to the one end and the other end and a voltage applied to the control gate, in the memory cells C having such a configuration, a charge is injected into the charge storage layer so that data can be written or the charge stored in the charge storage layer is extracted so that data can be erased.
Thus, the non-volatile semiconductor memory device 501 having the memory cells C can write and read out data into and out of a predetermined memory cell C, or erase the data written into the memory cell C by adjusting values of voltages respectively applied to the first bit line L1, the second bit line L2, the common word lines 502a to 502f, and the P-type memory well W503a to W503d. 
FIG. 13 illustrates respective values of voltages applied to portions when data is written into only the memory cell C arranged in the first row and the first column in the P-type memory well W503a in the first column among the plurality of memory cells C and data is not written into all the other memory cells C. For convenience of illustration, the memory cell C into which data is written is referred to as a selected memory cell C1, and the memory cell C into which no data is written is referred to as a non-selected memory cell C2. The common word line 502a to which the selected memory cell C1 is connected is referred to as a selected common word line 515, and the first bit line L1 and the second bit line L2 to which the selected memory cell C1 is similarly connected are referred to as a selected first bit line L1a and a selected second bit line L2a. On the other hand, the common word lines 502b, 502c, 502d, 502e, and 502f to which only the non-selected memory cells C2 are connected are referred to as a non-selected common word line 516, and the first bit line L1 and the second bit line L2 to which only the non-selected memory cells C2 are similarly connected are referred to as non-selected first bit lines L1b and L1c and non-selected second bit lines L2b and L2c. 
In this case, 0[V] is applied to each of the P-type memory wells W503a to W503d. Description is first made by paying attention to the P-type well W503a (hereinafter merely referred to as a selected byte) in which the selected memory cell C1 is arranged, and description is then made by paying attention to the P-type memory wells W503b to W503d (hereinafter merely referred to as non-selected bytes) in which only the non-selected memory cells C2 are arranged. In practice, in a selected row in which the selected common word line 515 is arranged, a writing gate voltage of 12[V] is applied to the selected common word line 515, and a writing voltage of 0[V] is applied to each of the selected first bit line L1a and the selected second bit line L2a. Thus, the selected memory cell C1 has its control gate to which the writing gate voltage of 12[V] is applied from the selected common word line 515 while having its one end and the other end to which the writing voltage of 0[V] can be applied from the selected first bit line L1a and the selected second bit line L2a. Thus, the selected memory cell C1 can enter a state where data is written thereinto because a voltage difference occurring between the control gate and a channel region becomes large, and as a result a quantum tunnel effect is produced so that a charge is injected into a charge storage layer.
In this case, in the selected byte, a writing inhibition voltage of 6[V] is applied as an intermediate voltage to the non-selected first bit line L1b and the non-selected second bit line L2b. Thus, the non-selected memory cell C2 connected to the non-selected first bit line L1b and the non-selected second bit line L2b in the selected byte has its control gate to which the writing gate voltage of 12[V] is applied from the selected common word line 515 while having its one end and the other end to which the writing inhibition voltage of 6[V] is applied from the non-selected first bit line L1b and the non-selected second bit line L2b. Thus, the non-selected memory cell C2 can enter a state where data is not written thereinto because a voltage difference occurring between the control gate and a channel region becomes small and as a result, a quantum tunnel effect is not produced so that no charge is injected into a charge storage layer. Thus, in a first area AR501 where the selected byte and the selected row intersect each other, data is written into only the selected memory cell C1 and is not written into the other non-selected memory cells C2.
On the other hand, in a non-selected row, a writing inhibition gate voltage of 0[V] is applied to the non-selected common word line 516. Thus, in a second area AR502 where the selected byte and the non-selected row intersect each other, the non-selected memory cell C2 connected to the selected first bit line L1a and the selected second bit line L2a has its one end and the other end to which the writing voltage of 0[V] is applied from the selected first bit line L1a and the selected second bit line L2a while having its control gate to which the writing inhibition gate voltage of 0[V] is applied from the non-selected common word line 516. Thus, the non-selected memory cell C2 can enter a state where data is not written thereinto because the control gate and a channel region have the same voltage and as a result, a quantum tunnel effect is not produced so that no charge is injected into a charge storage layer.
In the second area AR502, the non-selected memory cell C2 connected to the non-selected first bit line L1b and the non-selected second bit line L2b has its one end and the other end to which the writing inhibition voltage of 6[V] is applied from the non-selected first bit line L1b and the non-selected second bit line L2b and has its control gate to which the writing inhibition gate voltage of 0[V] is applied from the non-selected common word line 516. Thus, the non-selected memory cell C2 can enter a state where data is not written thereinto because a voltage difference occurring between the control gate and a channel region becomes small and as a result, a quantum tunnel effect is not produced so that no charge is injected into a charge storage layer.
A non-selected byte will then be paid attention to. In this case, in the non-selected byte, a writing inhibition voltage of 12[V] is applied to a non-selected first bit line L1c and a non-selected second bit line L2c. Thus, each of the non-selected memory cells C2 in a third area AR503 where the non-selected byte and the selected row intersect each other has its control gate to which the writing gate voltage of 12[V] is applied from the selected common word line 515 while having its one end and the other end to which the writing inhibition voltage of 12[V] is applied from the non-selected first bit line L1c and the non-selected second bit line L2c. Thus, the non-selected memory cell C2 can enter a state where data is not written thereinto because the control gate and a channel region have the same voltage and as a result, a quantum tunnel effect is not produced so that no charge is injected into a charge storage layer.
Each of the non-selected memory cells C2 in a fourth area AR504 where the non-selected row and the non-selected byte intersect each other has its control gate to which the writing inhibition gate voltage of 0[V] is applied from the non-selected common word line 516 while having its one end and the other end to which the writing inhibition voltage of 12[V] is applied from the non-selected first bit line L1c and the non-selected second bit line L2c. Thus, the non-selected memory cell C2 can enter a state where data is not written thereinto because a voltage value on the side of the control gate becomes smaller than a voltage value on the side of a channel region and as a result, a quantum tunnel effect is not produced so that no charge is injected into a charge storage layer.
Thus, in the non-volatile semiconductor memory device 501, data can be written, among the plurality of memory cells C arranged in a matrix, into only the predetermined selected memory cell C1 by adjusting each of values of the voltages applied to the common word lines 502a to 502f, the first bit line L1, and the second bit line L2.